The present invention relates to the field of analog-to-digital converters (ADC""s), and in particular, to a subranging ADC architecture that includes switches in a ladder arrangement.
Analog-to-digital converters (ADC""s) are useful in digital signal processing applications as well as video, imaging, and digital communication applications. An ADC takes an analog input and converts it into a digital code, i.e. xe2x80x9cdigitizesxe2x80x9d the analog signal. ADC""s can be designed in a variety of ways, using various analog and digital components such as comparators, sample-and-hold circuits, counters, as well as others.
A typical ADC circuit may include a series of reference signals (e.g. reference potentials), a comparator, and some switching logic. The switching logic selectively routes reference signals to the comparator. The comparator compares the reference signals to the analog input signal. The comparator output changes logic states as a result of the comparison of the reference signal to the analog input signal. The digital output code results from encoding the output of multiple comparators.
A xe2x80x9cflashxe2x80x9d type of ADC circuit includes a series of reference signals, encoding logic, and multiple comparators. Each reference signal has a corresponding comparator (2Nxe2x88x921 comparators for an N-bit digital code and 2N+1 comparators for an N-bit digital code with overrange). Each comparator outputs a logic value depending on whether the analog input signal has a value that is higher or lower than its associated reference value. All reference signals are simultaneously compared to the analog input signal by their corresponding comparator. The output of every comparator is received by the encoding logic which determines the digital code corresponding to the analog signal.
A xe2x80x9csubrangingxe2x80x9d type of ADC circuit includes a series of reference signals, encoding logic, and multiple comparators, similar to the xe2x80x9cflashxe2x80x9d type of ADC. Flash ADCs offer high speed, digitizing an analog input signal in a single clock cycle. In contrast, a xe2x80x9csubrangingxe2x80x9d architecture converts the analog input signal into a digital code in two steps. A coarse comparison is followed by a fine comparison for the subranging ADC. The subranging ADC therefore requires two-clock-cycles to complete a conversion of the analog input signal to a digital code. This is considered a disadvantage compared to the flash ADC which converts the analog input signal to a digital code in a single step. However, in a subranging ADC, the number of comparators required for a conversion is 21+(N/2)xe2x88x921 comparators for an N-bit ADC, which is much less than that of the flash ADC. For example, an 8-bit flash ADC requires approximately 256 comparators, while an 8-bit subranging ADC requires approximately 32 comparators. The reduced number of comparators for a subranging ADC results in less chip area taken up on the integrated circuit than for a flash ADC. The reduction in chip area required by the subranging ADC is considered an advantage over the flash ADC.
The outputs of the comparators in a flash ADC and a subranging ADC generate a code called xe2x80x9cthermometer code.xe2x80x9d The thermometer code is based on the architecture of both flash and subranging ADCs. When the tap point of a particular comparator is below the level of the input signal, the particular comparator outputs a high logic level. When the tap point of a comparator is above the level of the reference signal, the comparator outputs a low logic level. Over an entire bank of comparators in a flash or subranging ADC, the outputs of the comparators below the reference signal should have a high logic level, and the outputs of the comparators above the reference voltage should have a low logic level.
Briefly stated, in accordance with the present invention an electronic circuit that converts an analog input to a digital signal includes a series xe2x80x9cstringxe2x80x9d of resistors that provides reference signals with ascending values across the string. The reference signals are organized in banks of reference signals, with each adjacent set sharing a major code boundary. A coarse bank of comparators compare the analog input to the major code boundary reference signals and provide a coarse logic output. Each bank of reference signals has a corresponding bank of switches, with each switch associated with a particular reference signal in the bank. All of the switches in a particular bank are closed or opened in unison when selected. A particular bank is selected based on the coarse logic output signal. The reference values corresponding to the selected bank are coupled to a fine bank of comparators, each fine bank comparator. comparing the analog input signal to one of the selected reference values. The fine bank of comparators output a fine logic output that corresponds to one of a thermometer code and a reverse thermometer code. The switches that couple the reference values to the fine bank of comparators are arranged in a xe2x80x9cladder-flipxe2x80x9d architecture, where switches in adjacent banks share common junction nodes to one of the comparators in the fine bank. The switches that are connected to a particular common junction node are equidistant about the common major code boundary. The DNL errors that occur as a result of switching between different comparators across major code boundaries are reduced.
According to a feature of the invention, an apparatus for producing logic outputs from an analog input voltage, includes: a reference voltage circuit that has a first set of reference values and a second set of reference values, the first and second set of reference values having a common reference value that corresponds to a major code boundary. The apparatus further includes: a coarse comparator that produces a coarse logic output that corresponds to a comparison between the analog input voltage and the common reference value and at least two fine comparators that produce fine logic outputs that correspond to a comparison between the analog input voltage and a selected one of the first and second sets of reference values, the fine logic output corresponding to a fist code type when the first set of reference values is selected and corresponding to a second code type when the second set of reference values is selected, the second code type being different from the first code type whereby differential nonlinearity errors across the major code boundary are minimized.
According to another feature of the invention, a method of converting an analog input voltage to a digital code includes: comparing the analog input voltage to a major reference value that corresponds to a major code boundary in a series of reference values and producing a coarse logic output in response to the comparison of the analog input voltage to the major reference value, the coarse logic output indicating whether the analog input voltage is one of higher and lower than the major reference value. the method further includes: selecting one of a first and second bank of reference values in response to the coarse logic output, selecting the first bank when the analog input voltage is higher than the major reference value and selecting the second bank when the analog input voltage is lower than the major reference value, comparing the analog input voltage to the selected bank of reference values, producing a fine logic output in response to the comparison between the analog input voltage to the selected bank of reference values, the fine logic output being a first code type when the selected bank is the first reference bank and a second code type when the selected bank is the second reference bank, the first code type being different from the second code type, and producing the digital code in response to the coarse logic output and fine logic output wherein errors occurring in the digital code are minimized.
According to yet another feature of the invention, an apparatus for converting an analog input voltage to a digital signal includes a coarse comparison means for comparing the analog input voltage to a voltage of a common reference node to produce a coarse output. An ordered set of junction nodes is included having associated discrete voltages arranged in an order. Junction means are also included for providing discrete voltages corresponding to an ordered set of junction nodes arranged in an ascending order. A fine comparison means compares the analog input voltage to the associated discrete voltages to produce a fine output. The fine comparison means is arranged in an ascending order such that each of the fine comparison means has a unique corresponding junction node of the ordered set of junction nodes. The apparatus also includes means for selecting one of a first and second set of reference nodes that have a common major code boundary corresponding to the common reference node. The apparatus further includes means for selectively coupling the ordered set of junction nodes to the selected one of a first and second set of reference nodes such that the first set of reference nodes is coupled to the ordered set of junction nodes in an ascending order when selected, matching the ascending order of the second set of comparison means. The second set of reference nodes is coupled to the ordered set of junction nodes in a descending order when selected, opposite the ascending order of the second set of comparison means whereby differential nonlinearity errors occurring at the major code boundaries are minimized. The apparatus further includes means for producing the digital signal in response to the coarse output and fine output.